This invention relates generally to a method and pressure jetting machine for processing semiconductor wafers, and more specifically to a method and pressure jetting machine which improves the flatness of semiconductor wafers while providing a polished front surface and a damaged back surface suitable for inducing extrinsic gettering during subsequent processing of the wafer.
Semiconductor wafers are generally prepared from a single-crystal ingot, such as a silicon ingot, which is trimmed and ground to have one or more flats for proper orientation of the wafer in subsequent procedures. The ingot is then sliced into individual wafers which are each subjected to a number of wafer shaping or processing operations to reduce the thickness of the wafer, remove damage caused by the slicing operation, and to create a highly reflective surface.
In conventional wafer shaping processes, the peripheral edge of each wafer is first rounded, such as by an edge grinding operation, to reduce the risk of wafer damage during further processing. Next, a substantial amount of material is removed from the front and back surface of each wafer to remove surface damage induced by the slicing operation and to make the opposing front and back surfaces flat and parallel. This removal of material is accomplished by subjecting the front and back surfaces of the wafers to a conventional lapping operation (which uses a lapping slurry comprising abrasive particles), or a conventional grinding operation (which uses a disc with abrasive particles embedded therein), or even a combination of both lapping and grinding operations. The wafers are then etched by contacting each wafer with a chemical etchant to further reduce the thickness of the wafer and remove mechanical damage produced by the lapping and/or grinding operation.
Finally, the front surface of each wafer is polished, using a polishing pad and a polishing slurry comprising abrasive particles and a chemical etchant, to remove a small amount of material from the front surface of each wafer. The polishing operation removes damage induced by the etching operation and produces a highly reflective, damage-free front surface on each wafer.
In determining the quality of the processed semiconductor wafer, the flatness of the wafer is a critical parameter to customers since wafer flatness has a direct impact on the subsequent use and quality of semiconductor chips diced from the wafer. The flatness may be determined by a number of measuring methods. For example, "Taper" is a measurement of the lack of parallelism between the unpolished back surface and a selected focal plane of the wafer. "STIR", or Site Total Indicated Reading, is the difference between the highest point above the selected focal plane and the lowest point below the focal plane for a selected portion (e.g., 1 square cm.) of the wafer, and is always a positive number. "SFPD", or Site Focal Plane Deviation, is the highest point above, or the lowest point below, the chosen focal plane for a selected portion (e.g., 1 square cm.) of the wafer and may be a positive or negative number. "TTV", or Total Thickness Variation, which is frequently used to measure global flatness variation, is the difference between the maximum and minimum thicknesses of the wafer. TTV in the wafer is also an important indicator of the quality of the polish of the wafer.
With respect to wafer flatness, the conventional method of processing a semiconductor wafer described above has a number of disadvantages. For example, etching the wafer in an acid-based etchant generally deteriorates the flatness produced by the lapping or grinding operation. In addition, the flatness performance of the single-side polishing operation is inconsistent, depending primarily on the shape of the wafer being polished. The single-side polishing operation is a single-side planarization process, which limits its flattening capability.
In order to overcome this limitation and meet the demand for flatter wafers, a double-side polishing operation has become the polishing process of choice by wafer manufacturers. In a double-side polishing operation, the front and back surfaces of each wafer are polished simultaneously so that removal of material occurs uniformly on both sides of the wafer. Typically, equipment used for double-side polishing operations includes opposing rotating pads (one corresponding to each side of the wafer) that rotate in opposite directions while working the polishing slurry against the wafer. However, double-side polishing operations produce wafers generally having equally polished front and back surfaces, with little damage remaining on the back surface. This has been found to be undesirable to customers because of the lack of extrinsic gettering sites on the back surface of the wafers. Rather, these customers prefer wafers having a polished front surface and a back surface having subsurface damage to induce extrinsic gettering in subsequent processing operations.
Also, in conventional processes where the surfaces of the wafer are subjected to single-side polishing operations, the back surface of the wafer is subjected to a damaging operation before rapid thermal annealing (RTA) for thermal donor annihilation, if required, and before the single-side polishing. RTA tends to reduce the amount of damage previously induced in the back surface and also induces warp during the single-side polishing operation.